1. Field of the Invention
The present invention generally relates to a high-temperature superconductive device, and more particularly, to a high-temperature superconductive device characterized by an electrode structure which reduces the inductance of ramp-edge junctions used for various digital processing circuits such as a superconductive sampler for measuring a high speed signal and an A/D converter circuit for measuring a high speed or a very small signal.
2. Description of the Related Art
An oxide superconductor such as a Yttrium system superconductor becomes superconductive at a temperature higher than liquid nitrogen temperature. The oxide superconductor requires a less complicated cooling system than does a conventional metal superconductor that requires cooling down to liquid helium temperature. Various applications of the oxide superconductor are recently under intensive study. Japanese Laid-Open Patent Application No. 2000-353831, for example, discloses an example of such studies.
As one of the characteristics of the oxide superconductor, superconductive current easily flows along a Cu—O plane in crystals made of copper (Cu) and oxygen (O). It is preferable that any junction be formed in parallel to the Cu—O plane. The ramp-edge type junction is proposed as such a junction.
There are two types of ramp-edge junctions known in the art. One type of ramp-edge junction includes a barrier layer made of deposited film. The other type of ramp-edge junction includes a barrier layer that is formed by modifying a surface with ion irradiation. Japanese Laid-Open Patent Application No. 2001-244511 and “Superconductor Sci. Tech.”, Vol. 14, pp. 1052-1055, 2001, for example, disclose such a ramp-edge junction. Especially, a ramp-edge type interface-modified junction is drawing attention.
The ramp-edge type interface-modified junction is formed as follows. A slant junction interface is formed on a lower electrode. The surface of the slant junction interface is damaged by ion irradiation. An upper electrode is deposited on the slant junction interface. The critical current density Jc needs to be controlled to realize accurate operation of a circuit. It is desired that the junction properties of high-temperature superconductor devices on a substrate be uniform.
The lower electrode layer is fabricated to form ramps in four directions. Ions are applied to the substrate perpendicular thereto to form a uniform damaged layer on the ramps. The device is heated in an oxygen environment, and an upper electrode is deposited. As a result, interface-modified ramp-edge junctions having the same critical current Jc are formed in the four directions. According to the above arrangement, a high-temperature superconductive circuit having uniform properties can be fabricated. Interface-modified ramp-edge junctions may be formed in one, two, or three directions in the same manner.
A single flux quantum (SFQ) circuit can operate at very high speed and with low power consumption. When a SFQ circuit is designed and fabricated, the product (L×Ic product) between the inductance L and the critical current Ic in a superconductive loop including a Josephson junction needs to be approximately equal to a flux quantum φ0 (=2.07×10−15 Wb) or φ0/2.
In this case, the greater the product (Ic×Rn product) between the critical current Ic and normal-state resistance Rn of the junction used for the SFQ circuit is, the smaller the width of a SFQ pulse is. As a result, the device operates at higher speed. In the case of a high-temperature superconductive interface-modified junction, the Ic×Rn product can be made high by increasing the critical current density Jc.
FIG. 7 is a graph showing the relation between the Ic×Rn product and Jc as actual data. The graph indicates that the Ic×Rn product and Jc relate as follows:Ic×Rn=Jc0.2, orIc×Rn=Jc0.5.The index depends on the state of the high-temperature superconductive interface-modified junction. If Jc is increased, the Ic×Rn product can be increased.
A conventional superconductive junction device having the interface-modified ramp-edge junction is described below with reference to FIGS. 8A-8G.
As shown in FIG. 8A, a lower electrode layer 52 made of YBCO (YBa2Cu3O7-x) and an interlayer insulation layer 53 made of CeO2 are deposited on a LSAT substrate 51 in that order using a pulsed laser deposition method.
As shown in FIG. 8B, photoresist is applied on the interlayer insulation layer 53. The applied photoresist is exposed, developed, and processed by reflowing thereby to form a photoresist pattern 54. Ar ions 55 are applied to the layers for ion milling using the photoresist pattern 54 as a mask. Thus, a ramp-edge structure is formed.
As shown in FIG. 8C, Ar ions 57 are applied to exposed ramp 56 in a direction perpendicular to the LSAT substrate 51 thereby to form a damaged layer 58.
As shown in FIG. 8D, an upper electrode layer 59 made of YBCO is deposited using the sputtering method.
As shown in FIGS. 8E through 8G, a bridge unit 60 is formed by processing the upper electrode layer 59 with ion milling. Thus, the basic structure of the interface-modified ramp-edge junction is formed. FIG. 8E is a top view of the interface-modified ramp-edge junction. FIG. 8F is a cross-sectional view along the one-dot chain line A-A′ shown in FIG. 8E. FIG. 8G is a cross-sectional view along the one-dot chain line B-B′ shown in FIG. 8E.
As described above, the ramps are formed in the four directions by processing the lower electrode layer, and a uniform damaged layer is formed on the ramps by applying the ions in a direction perpendicular to the substrate. As a result, the interface-modified junctions having the same critical current density Jc in the four directions can be formed. Since the critical current densities Jc in a circuit are equal to each other, the circuit can operate correctly.
FIGS. 9A-9C are schematic diagrams for explaining an interface-modified ramp-edge junction in which a ground plane on the substrate is provided thereby to reduce inductance. FIG. 9A is a top view of the interface-modified ramp-edge junction. FIGS. 9B and 9C are cross-sectional views along the one-dot chain lines A-A′ and B-B′, respectively.
As shown, a ground plane 61 made of YBCO and an insulation layer 62 made of CeO2 are deposited on a LSAT substrate 51 in that order. After forming the layers, the same steps as shown in FIGS. 8A-8G are performed. The inductance can be reduced by providing the ground plane 60.
As described above, the inductance L of the circuit and the critical current Ic of the Josephson junction need to be determined so that the L×Ic product satisfies the condition (L×Ic<φ0). Since the ramp-edge junction is substantially flat with the end of the lower electrode layer being slanted, the upper electrode layer 59 and the lower electrode layer 52 need to be separate by 1 μm or more.
Currently used lithography causes the upper electrode layer 59 and the lower electrode layer 52 to be separated by 3 μm or more, and as a result, the bridge unit 60 is formed. Accordingly, a parasitic inductance is made in series with the junction. If the critical current density Jc of the Josephson junction is made high to increase the Ic×Rn product, the width of the junction, therefore the width W of the bridge unit 60 need to be made small to obtain the same critical current Ic.
If the width W of the bridge unit 60 is made smaller, the ratio of the length thereof to the width becomes greater. As a result, the parasitic inductance becomes greater.
For example, in the case of fabricating a Josephson junction having the same critical current Ic under a condition in which the thickness of the electrode, the length of the bridge unit 60, and the sheet inductance remain unchanged, if the critical current density Jc is made N times, the width of the junction needs to be 1/N times. Thus, the parasitic inductance is made N times.
As a result, if the critical current density Jc is made higher, the loop inductance of the superconductive loop including the Josephson junction is increased. Accordingly, it becomes difficult for the L×Ic product to satisfy the above condition (L×Ic<φ0). The SFQ circuit cannot operate.
To avoid this problem, when a circuit is designed, a junction of high Jc is not used. The inductance is determined based on a sub-circuit in the circuit, the L×Ic product of which needs to satisfy the most severe condition. The width of the junction is made great so as to reduce the effect of the parasitic inductance.
However, if the width of the junction is made great to reduce the effect of the parasitic inductance, the critical current density Jc of the Josephson junction cannot be made great, and the Ic×Rn product becomes relatively small. As a result, the width of the SFQ pulse is made wide which results in low operating speed and unstable operation (jitter) of the SFQ circuit.